Miniaturization of the copper features in electronic circuits results from placing interconnections closely with a high packing density. As a result, crosstalk in HDI PCB substrate comes at play because of the increased coupling between the adjacent signal lines.
HDI substrates are multi-layer, high-density circuits with features including the fine line and well-defined space patterns. The increasing adoption of HDI substrates enhances the overall functionality of PCBs and limits the operational area.
One of the key factors that differentiate HDI PCB design from the rest is their unique design that comprises multiple layers of copper filled microvias. These multi-layers of microvias enable vertical interconnections. Further, HDI substrates offer the advantages of having higher integration levels and better placement of components on both sides. Additionally, HDI boards consist of a higher number of I/Os in smaller geometries. Other features of HDI substrates include faster transmission of signals and a significant reduction in signal loss and delays.
The recent technology adopted for the preparation of HDI boards deals with the miniaturization of components and the adoption of high-end devices. However, challenges such as crosstalk can severely affect the performance of HDI boards. Thus, the adoption of advanced PCB design services becomes critical to avoid crosstalk in HDI boards.
Crosstalk is an unintentional electromagnetic coupling among the traces on a PCB (even though they are not in physical contact with each other). Moreover, electromagnetic field disturbance can take place in PCBs due to external interference. Crosstalk occurs when there is coupling (capacitive and inductive) of energy from the aggressor signal to the victim signal (typically, two tracks close to each other) in terms of the interference of electric and magnetic fields. The electric field is coupled via mutual capacitance between the signals. On the other hand, the magnetic field is coupled via mutual inductance between the signals. Traces running parallel on the same layer or running parallel vertically between two layers are susceptible to crosstalk.
Crosstalk generates undesirable effects that affect clock, periodic signals, system-critical nets like data lines, control signals, and I/Os. Additionally, the affected clock and periodic signals create serious functionality concerns for working PCB and assembly components. Due to the crosstalk effect, the voltage and current levels outreach the threshold level of the logic devices. This can be interpreted as a false logic state when it reaches the receiver. A designer needs to work smartly to avoid the error caused by these erroneous logic states. Crosstalk can also affect analog signals by adding noise. This noise could come through the power rails.
Also read: Happy Holden Discusses HDI
Crosstalk in HDI substrates is reduced by the shorter coupled lengths and by the lower dielectric constant by as much as 50 percent. Other factors that can limit crosstalk in HDI substrate include,
- Use of lower Dk materials.
- The lower dielectric constant of the HDI PCB material system may allow a board to shrink up to 28 percent.
- The thinner the distance to the reference plane, the lower the near-end crosstalk will be.
HDI miniaturization provides shorter interconnect lengths. If a lower dielectric constant material is used, then crosstalk in HDI substrates can be reduced. Eric Bogatin, Signal Integrity Evangelist at Teledyne LeCroy, provides the following example: “A typical line-width in HDI technology is 3 mils (75 microns). The figure below shows the characteristic impedance of 3-mil-wide traces for various dielectric thicknesses.
The dielectric thickness will be less for a lower dielectric constant. This means a lower dielectric constant material system will either result in less crosstalk for the same spacing, or the traces can be moved closer together and have the same amount of crosstalk.”
Eric Bogatin continues, ”In the two cases studied, the line-width was 3 mil, and the dielectric thickness was adjusted so that for the two different dielectric constants, the line impedance was the same. From these curves, it can be seen that if the routing pitch is crosstalk constrained, the lower dielectric constant of the HDI material system may allow a board to shrink up to 28 percent.
For coupled lengths less than the saturation length, the magnitude of the near-end voltage noise will scale with length. The saturation length will depend on the rise time. For a rise time of 1 nanosecond, the saturation length with an effective dielectric constant of 2.5 is about 7.6 inches, which would include many of the traces in a small card application. The relative coupled near-end noise would be given by:
Crosstalk in HDI substrates is reduced by the shorter coupled lengths and by the lower dielectric constant by as much as 50 percent. Shorter trace lengths will radiate less, and traces with thinner dielectric will also radiate less. The below example shows that the shorter coupled length leads to less mutual inductance (Lm), and thinner traces leads to less mutual capacitance (Cm).
The thinner the distance to the reference plane, the lower the near-end crosstalk will be, or the same crosstalk for a longer coupled length. With length reductions of 2x and dielectric thickness reductions of 2x over conventional boards, the radiated field from HDI signal loops might be reduced by as much as 4x, which is 12dB.”
Eric Bogatin further states, “If the entire board is HDI, rather than just a few outer layers, controlling the return path can be a bigger challenge than in through-hole boards.”
“You have to pay attention to the same issues to deal with crosstalk in HDI substrates:
- Providing a continuous return path
- Engineering controlled impedance interconnects
- Route in a linear, daisy chain path with minimal stub lengths
- Control reflection noise with terminations
- Manage via to via crosstalk by the return path control
- Use low inductance capacitors connected to the IC pins
In conjunction with a through-hole core, HDI interconnects can be incredibly valuable.”
Also read: The History of High Density Interconnect
The following measures can be adopted to avoid crosstalk in an HDI substrate:
In integrated circuits, capacitive and inductive coupling cause crosstalk. Inductive coupling is concerned with mixed input-output circuitry, while capacitive coupling affects the switching speed of the circuitry. Here are some considerations for circuit design to reduce the capacitive coupling, thus crosstalk:
- Do not route two parallel wires over a long distance in the same layer. Also, the layers adjacent to traces should be perpendicular.
- Route ground or power between two sensitive signal lines.
- Separate sensitive nodes from full-swing signals and avoid floating nodes. Nodes sensitive to cross-talk issues should be provided with devices to minimize impedance.
- Use differential signaling on sensitive low-swing wiring networks.
- Crosstalk between the signal layers in different layers can be reduced by designing a ground layer between the signal layers.
- On inner layers, when signals are placed between two ground layers, the capacitive coupling is reduced. Read how can we reduce parasitic capacitance in PCB layout.
- PCB designers can use optical interconnections to reduce EMI and crosstalk. Read more about PCB design guidelines for EMI and EMC.
澳洲5玩法5 Chapters - 52 Pages - 60 Minute Read
- Planning your stack-up and microvia structure
- Choosing the right materials
- Signal integrity and controlled impedance in HDI
- Manufacturing considerations for higher yields
The ground plane is the low impedance return path for the signal conductors. Designers must reduce the area between the ground and signal conductor to minimize the loop. A reduced loop area can reduce the inductance.
In the ground plane of a multi-layer PCB, there must be a large number of vias, which increases the via density. In a group of adjacent connections, the inductive coupling could occur if the ground and signal layers share a common area. Designers must route a wide loop around the slot to avoid inductive coupling and thus reduce crosstalk.
A via surrounded by a closed ground wall shortening the planes acts as an electrical boundary. It reflects all the energy and develops half-wave resonances based on the diagonal dimension of the closed boundary.
Provide return path as close as possible to signal path
When using connectors and cables, special care must be given to ground pins and wires since we don’t want to increase the current return loop area. The loop area can be minimized by moving the ground pin close to the signal pin.
Avoid nested loops using ground pins
While designing cable inputs, running different conductors nearby may generate coupling issues. Using the same pin for the ground path from several signals creates nested loops with high mutual inductance. The PCB designers must consider separate ground return pins, which should be in a minimum distance from the signal pins to reduce the inductive coupling.
Every layer interconnect (ELIC) is an advanced stackup construction method in which a connection can be started or ended in any layer. Circuit connections are made in the initial buildup itself, so there will be only less requirement of blind and buried vias. This gives the designers a large routing space in the layers. However, there are some limitations when it comes to the routing of an ELIC construction.
The designers should care about the signal layer; no two signal layers should be adjacent. Place the ground layer between all signal layers. As the ELIC construction allows connection between any layer, it is easy to build up in a symmetrical arrangement.
To reduce crosstalks and to increase routing density, a boulevard structure via placing is used. Designers can use several types of via placement structures in BGA according to their application for via-to-via crosstalk. A boulevard structure suitable for reducing crosstalk and increasing routing space is shown above. Let us discuss that.
Region 1 consists of the outer rows, where the number of rows varies from 4 to 6 as per the design rules. Region 2 consists of all the inner rows. Region 3 is the transition between inner and center rows, and region 4 is the center.
As depicted above in the region 1 a, the traces are routed on layer 2 to the maximum routing density using a 1:2 microvia. To increase the number of vias or to reduce the spacing between them, designers can bring the vias closer to the ball pad without exceeding the minimum distance required. Also, designers can change the orientation of the via-ball pad structure. Such arrangements are capable of increasing routing space and reduce crosstalk between vias.
After routing outer layer BGA pins using 1:2 microvias in the region 1, rows from 4 to 6 in the region 2 b are routed on layer 3 with maximum routing density using 1:3 skip-vias. The skip-via allows a connection from Layer 1 to Layer 3 without using a pad on Layer 2. This pattern can also be changed by moving the via closer to the ball pad and adjusting the angle to reach the required size.
Region 3 c is the transition region between region 2 and region 4. It can use any of 1:2 and 1:3 microvias as per the routing strategy. Region 4 d is the leftover region. Usually, the central region is occupied by ground and power pins. To allow the greater ground plane fill on layer 1, vias cannot be placed in the exact center of the BGA.
Like this, dividing the BGAs into regions to place vias not only increases the routing density but also reduces the number of layers. If the nets end in blind vias instead of via stubs, via to via crosstalk can be reduced. To know more about via stubs read how via stubs affect signal attenuation and data transfer rates.
Note: In the above BGA pattern example, we have used orthogonal short dog-bone structure. You can use other angle adjustments also based on the via sizes.
Learn How To Breakout a .5mm BGA
We all know that conventional PCB designs use a dedicated power plane. But as soon as the density and the number of voltage rails increase, the need for split planes arises. We can use two orthogonal layers to distribute PWR as a ‘mesh structure’. And by placing signals between the different voltages, we can increase the number of split planes for up to eight different voltage rails. It is called a ‘dual offset coplanar stripline with separate GND reference. This structure provides lower crosstalk and voltage to all the components from LAYER 2 to LAYER N-1 using only a blind via.
Crosstalk can be described based on two figures of merit, named as, Near-End Crosstalk (NEXT) coefficient and the Far-End Crosstalk (FEXT) coefficient. Both terms give the ratio of near and far-end noises generated on the noiseless line in a uniform pair of transmission lines when the ends are terminated in their characteristic impedances. It is a measure of the typical crosstalk noise that would be observed.
The characteristic impedance can be defined by dielectric thicknesses, line width, and dielectric constant, while the space between the adjacent traces tells the crosstalk. These electrical qualities scale with geometry. For example, if every feature in the cross-section is reduced by a factor of 5, the characteristic impedance and NEXT and FEXT values will not change. Check the following geometric features for a conventional PCB, and an HDI interconnect. They are reflecting the same performance. Read the advantages of HDI PCBs and their applications for better understanding.
|Geometric features||Conventional PCB||HDI|
Sometimes, designers think that scaling doesn’t give any electrical advantage to HDI designs. Because scaling all the features down still reflects the same electrical performance. It is valid for scaling down a cross-section of uniform signal lines. Still, there are two non-scaling terms that affect electrical performance in HDIs:
- Short length of the HDI interconnects
- Use of non-reinforced laminates with a lower Dk in HDI interconnects
The above features provide shorter and controlled time delay and less crosstalk since some electrical properties do not scale with smaller feature sizes.
Impact of stackup geometry and coupling length on HDI crosstalk
The magnitude of far-end crosstalk also depends upon the stackup geometry and the coupling length. It varies like:
FEXT = k (Len/RT)
Where FEXT = Far-end crosstalk coefficient
k = Coupling between two lines (victim and aggressor) in ns/inch
Len = Coupling length (inches)
RT = Rise time of the signal (ns)
Far-end noise is generated due to the inconsistency in the dielectric layer at the surface interface. This non-uniform nature of dielectric constant increases the far-end noise. However, only surface traces experience the far-end noise, and the buried traces (like in stripline) experience only near-end noise. It is worth noticing that near-end noise saturates in magnitude and does not scale as coupling length increases. It only happens if the coupling length is more than the critical length.
Eliminating crosstalk in HDI substrate before EMC testing provides PCB designers with a faster time to market period for their products. Crosstalk is one of the critical parameters that creates signal integrity issues, if not treated well. It can directly lead to distortion in the receiver signal. Crosstalk amount depends upon the line spacing, signal rise time, amplitude of the aggressor signal, and board and trace geometry. Thus, it should be a prime concern among designers to minimize the effect of crosstalk in HDI substrates.
澳洲5开奖官网3 Chapters - 12 Pages - 20 Minute Read
- Impedance discontinuities
- Reflections, ringing, overshoot and undershoot
- Via stubs