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Every PCB should be designed in such a way that the overall cost and chances of potential DFM issues can be minimized. It is done by adopting the optimized PCB design services for DFM checks. DFM is short for ‘Design for Manufacturability’. The designer/manufacturer can realize a manufacturable PCB in terms of quality and cost by following the DFM guidelines religiously.

DFM is a process of arranging PCB layout to resolve DFM issues that may arise during PCB assembly and PCB fabrication. For sure, DFM supports multiple iterations in the PCB design but it should be done only in the early production stages.

Optimizing a PCB for fabrication issues creates the requirement of Design for Fabrication (DFF). In the same way, PCB assembly problems are targeted by adopting the Design for Assembly (DFA) process. So, it is quite understood that DFM is an amalgamation of DFA and DFF. The term DFMA (design for manufacturing and assembly) is occasionally used equivalently with DFM. Nowadays, PCB assembly and fabrication engineers can perform the DFM checks and DFM analysis to identify DFM issues. Initially, only those companies could perform DFM analysis that held strong financial support to purchase a costly DFM analysis software.

In this post, you will learn more about the following aspects of the possible DFM issues in a PCB:

• What is design for manufacturability or DFM in a PCB?
• What are the factors to design for manufacturability?
• 6 DFM issues designers should check before PCB manufacturing
• DFM checks for controlling DFM issues
• DFM tools to ease your PCB design

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DFM for PCB is a set of design guidelines that attempt to ensure its manufacturability. Imagine finding DFM issues in the fabrication and assembly process in the final stage. That would be a nightmare! DFM is not only a manufacturer guide to better fabrication and assembly but can also help designers. It’s true that manufacturers use DFM checks to look for issues and fix them. But very often, manufacturers do not intimate designers about the changes they made. And, sometimes even the changes made are not on the same page with the design and its performance or electrical requirements.

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DFM analysis identifies the PCB layout issues that can create manufacturing problems during assembly and fabrication. DFM issues are related to the PCB geometry, and most of the time, go undetectable during the DFM checks. Companies use specific DFM tools and DFM software based on their design requirement.

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If a PCB is performing appropriately and the design engineer is also satisfied with it, then why DFM checks? There are various reasons: cost of final PCB, design layout, and chances of future design failure.

• Theoretically, in cost terms, PCB designs submitted without DFM checks are less expensive than the designs with DFM checks. But it is better to pay a little extra so that the manufacturer could ensure whether the design is manufacturable or not.
• To sustain a PCB layout with DFM issues, CAM engineers edit the data to meet the design requirements. This is one primary reason that introduces signal integrity issues and EMI/EMC issues.
• PCBs assembled and tested efficiently, still fail. The main reason is that the design data still contained the DFM errors that were resolved in the prototype but were not implemented during the production.

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Avoiding DFM issues is a better approach than letting it ruin your PCB design and then looking for a remedy. DFM needs smart moves from the designer’s side. It is solving problems before they appear. DFM issues can be due to:

• Non-functional PCB design
• Board functions but not as intended (within the specification). It happens due to component mismatch and timing errors in a PCB.
• Random failure that does not reflect any connection with the possible situation

Keeping track of DFM rules and consistent DFM checks can help the designer to avoid the following DFM issues:

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To define acid traps, we need to know how traces are laid on the PCB surface. If any copper feature is bending anywhere below 90⁰ (acute angle), it may act as an acid trap during PCB fabrication. It happens before washing when residual acid gets collected in these trap areas and not cleared away. Due to these traps, the desired copper feature starts to erode (over-etching), creating an ‘open’ or lost connection. Avoiding acid traps is very important because today’s PCB traces are very thin, say 4 or 5 mils.

How to avoid acid traps? Refrain from laying the traces coming towards pads at acute angles. Keep it 45 or 90 degrees adjacent to the pad.

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Slivers are small free-floating wedges of copper (conductive) or solder mask (non-conductive) on the plane that redeposit to other copper pieces or expose copper and create shorts. And, if they are big enough to not float then they form an antenna, responsible for noise and other interferences within the board. Now, the question is, why do they create an antenna? Because they have no grounding hence act as a signal catcher.

How to avoid copper slivers? Slivers can be avoided by maintaining copper features around 0.004 inches. In the example given below, we are talking about the spacing between antipads. This trick is not 100% full-proof but greatly reduces the chances of copper redeposition elsewhere on the layer. This depends on the copper weight also. The higher the copper weight, the wider the connection area required.

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Thermals are the small copper spokes in a thermal relief pad, used to electrically connect it to the plane. Such thermals enable the thermal relief pads to disperse the heat effectively during the soldering process. In some cases, voids between the thermal and the plane or the pad can lead to an incomplete connection, minimizing the effectiveness of heat transfer. This, in turn, can lead to various functional problems. Such thermals affected by voids are called starved thermals.

Starved thermals may solder irregularly or take a longer time to reflow during the assembly process. Other problems that might result include overheating and heat damage to the board.

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Pins that are missing a clearance pad will connect to a plane layer. If clearance pads are not available from all plane layers for the pin, it will connect all of the voltage planes.

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Drill size is specified that exceeds the pad’s size being drilled and can result in a disconnect of the pin or short in a voltage plane. Read more about the annular ring here.

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Sometimes, designers forget to provide sufficient clearance between copper and PCB edge. If copper is too close to the edge then shorts can be created when current is applied to the panel between the adjacent layers. It happens due to the exposed copper around the perimeter of the board.

Design tip: This DFM issues can be avoided by routing keep-in shape DRCs for DFM checks.

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10 Chapters - 40 Pages - 45 Minute Read

What's Inside:

• Annular rings: avoid drill breakouts
• Vias: optimize your design
• Trace width and space: follow the best practices
• Solder mask and silkscreen: get the must-knows

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DFM checks are mandatory for designing a PCB with optimum manufacturability. Knowing and applying DFM checks can save you from the disastrous effects of potential DFM issues. It is like preventing the DFM issues before they pop up in your design and affect the PCB assembly process.

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The hole drilling process is the foundation for vias and the connectivity between different layers. Drilling is the most expensive, irreversible, and time-consuming process in the PCB manufacturing process. As soon as the number of holes increases, the check for drill-to-hole spacing becomes critical. Two significant aspects to be considered in the drilling process: aspect ratio and drill-to-copper clearance (drill to the nearest copper feature).

1.1 Aspect ratio: The ideal aspect ratio is 10:1 for through-holes and 0.75:1 for microvias. When the aspect ratio is larger, it becomes more difficult to achieve a reliable copper plating inside the vias. It will also add to the time for manufacturing and cost. Hence, the smaller the aspect ratio, the higher the PCB reliability. At Sierra Circuits, we offer an aspect ratio of 0.75:1 for microvias.

Aspect ratio (Through-Hole) = [(Thickness of the PCB) / (Smallest drilled hole)]

Since microvias don’t protrude through the entire board, the aspect ratio would be:

Aspect ratio (Microvias) = [(Drill Depth) / (Smallest drilled hole)]

1.2 Drill-to-copper: It is challenging because separate process tolerances impact it throughout the manufacturing process. The separate process tolerances include the glass weave and resin content in the PCB materials, PCB lamination thermal profile control, accuracy of the drill machines drill true position, the number of lamination cycles, and material type used. Achieving tight drill-to-coppers requires X-rays into the inner layers to get scaling information after lamination. Always check if your fabricator has that capability. To learn more about lamination voids, read lamination voids and delamination in PCB manufacturing.

How to handle drilling disaster: Problems like roughness inside the drill hole, resin smear, burrs, and nailhead can be avoided by adopting deburring and desmearing processes.

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Annular rings are one of the biggest concerns of PCB designers. You know that you may have placed your via right in the middle of the pad in the design files, but it might not be easy to get the same result in the physical world. Even though the designers calculate and place the perfect annular ring in their CAD design, manufacturing issues often cause vias to be drilled off-center. Another explanation could be that some layers may slightly shift during the lamination process. Or, the registration may not be 100% dead-center during the imaging process, and so on. These manufacturing issues can result in three different problems.

2.1 Undesired annular ring: If the PCB designer provides a wide annular ring area, the chances are that the via will be drilled approximately in the middle of the pad. Even though it will not be dead-center, this will still retain good electrical connectivity.

2.2 Tangency: If the PCB designer doesn’t provide a wide enough annular ring area, then the hole could almost end up touching the boundaries of the pad. This leads to an annular ring width that equals 0. Here, the drilled hole forms a tangent with the outer rim of the annular ring called tangency. This will lead to connection problems between the via and the copper traces.

2.3 Breakout: When the hole shifts over the copper pad, the drill bit might deviate outside the pad during the drilling process. This is what we call an annular breakout. Annular breakouts can lead to connection problems between the via and the layers. It also causes problems with component placement, solderability, and so on.

Design tips for annular rings: Getting the perfect annular rings predominantly depends on your PCB manufacturer. The minimum annular ring varies from manufacturer to manufacturer. So, it is always good to find out their capabilities before placing an order. Also, the annular ring depends upon the IPC spec you want to build the boards to, class 2, or class 3. Class 3 boards need more annular ring.

• As a quick inspection, check if the copper pads are present for plated drills on all copper layers.
• Check if the annular ring called out in fab can be maintained by the manufacturer.
• For Class 2, 90 degrees break out of the hole from land is allowed, provided the minimum lateral spacing is maintained. Read more about different design rules by IPC class 2 and class 3.
• For Class 3, the minimum internal annular ring cannot be less than 1 mil. The external annular ring cannot be less than 2 mils.

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8 Chapters - 23 Pages - 35 Minute Read

What's Inside:

• IPC guidelines for manufacturing defects
• IPC standards for assembly processes
• Common differences between the classes
• IPC documents to set the level of acceptance criteria

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Signal checks should be done for the parameters like conductor width, spacing requirements, and hole registration.

3.1 Conductor width: The width of the conductor traces becomes crucial as it directly impacts the functionality of a PCB. Additionally, increasing signal flow through PCB traces generates an immense amount of heat. Monitoring trace width also helps to minimize heat build-up that typically occurs on boards. Adequate conductor width helps to ensure the safe transmission of current without overheating and damaging the board.

Trace width calculation: Many manufacturers opt for their default trace width value available, which may not be suitable for high-frequency applications. Moreover, depending on the application, the trace width is varied, thus affecting the current carrying capacity of the trace. The maximum current carrying capacity for 2 oz copper with a temperature rise of 10°C is mentioned in this table.

IPC-2221 gives the formula for calculating the trace width for allowable current:

Width[mils] = A[mils^2]/(Thickness[oz]*1.378[mils/oz])

As per IPC-2221, for internal layers k = 0.024 and for external layers, k = 0.048.

The cross-sectional area A is calculated by the below-listed formula:

A[mils^2] = (I[Amps]/(k*(ΔT[deg. C])^ 0.44))^(1/0.725)

Where I is the current, k is a constant, ΔT is temperature rise, and A is the cross-sectional area of the trace.

During the design phase, you should consider the trace width as one of the most important parameters. It is essential to decide the adequate trace width to ensure the performance of the circuit board. This also helps to ensure the safe transmission of current without overheating and damaging the board.

Challenges with conductor width: The maximum current-carrying capacity of a copper trace usually differs from the theoretical value due to several factors. Some of the factors include the number of components, pads, and vias. Moreover, super large transient surges can lead to the burning down of a trace between pads during the initial supply of power or when modifications are implemented on traces. To avoid such complex issues, we prefer to increase the trace width.

Design tips for conductor width: It is highly preferred to calculate the PCB trace current-carrying capacity to decide the precise trace width. The minimum spacing is done to limit the excess of losses. Usually, the traces’ size on an outer layer shouldn’t be below 4 mils, as plating needs to be performed on these traces.

3.2 Line spacing: Spacing between traces helps maintain a distance between two traces, thus avoiding flashover or tracking between electrical conductors. Factors, such as voltage, application, and type of assembly, impact spacing requirements as well.

Line spacing clearance and creepage requirements: Clearance is defined as the minimum distance through the air (medium) between two conductors. Lower clearance among PCB traces can lead to overhead clearance, resulting in overvoltage. Furthermore, this over-voltage results in an arc between neighboring conductive traces on the PCB and surface breakdown due to high-voltage spike. The measurement of clearance depends on factors such as the PCB material, applied voltage, and temperature variations. For more detailed info, read the importance of PCB line spacing for creepage and clearance.

Creepage is defined as the shortest distance between two conductors on a PCB along the surface of the insulation material. Factors such as board material and environment conditions affect the creepage requirements. Several measures are implemented to avoid these errors, such as moving tracks and increasing the surface distance in your design. Designers can avoid spacing errors by adding a slot between traces or placing vertical barriers of insulation.

Design tips for line spacing: Spacing reduction can be achieved by adopting double-sided assembly and implementing insulating materials. Insulating materials act as a sheet barrier for high-voltage nodes. They also cover overexposed high-voltage leads.

• As most of the board components are SMDs, the circuits that require clearance can be placed on the top and bottom sides of the board.
• Try to keep high-voltage circuits on the top and low-voltage circuits at the bottom of the PCB.
• Tricks like V-groove, parallel-sided notch, or placing a slot in your design can effectively solve your creepage issues.

3.3 Hole registration: The hole registration is the displacement of the drilled hole from the target. The accuracy of the hole registration is evaluated by calculating the drilled hole from the target. Misregistration of the hole can lead to a violation of the minimum annular ring requirement, which should be avoided at any cost.

3.4 Missing copper: After designers generate an IPC netlist out of a schematic, that list should be purposefully used to avoid missing interconnections. These missing interconnections can result in missing copper that designers must check by themselves.

3.5. Unconnected or dangling lines: Unconnected lines may occur due to a high level of complexity in a PCB design. It is always difficult to locate unconnected lines. Unconnected lines can result in a hairline short defect that incurs during PCB manufacturing processes. Designers can themselves correct such errors by allowing a larger clearance between copper connections and pads.

Try our PCB Via Quiz

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Ideally speaking, the function of the solder mask is to cover all traces, i.e., to isolate solderable and non-solderable areas. But practically, there exists a tolerance that decides how close the solder mask can be to surface elements. Therefore, the clearances in densely-packaged designs cannot be increased arbitrarily. Generally, the all-over clearance should be half the conductor spacing width. There can be instances where it is not advisable or not even possible to apply a solder mask. For example, places where heat sinks are used, where the separation between pads are very small when a component is too close to drilling holes. These areas, where the solder mask is not applied, are usually defined by solder mask clearance restrictions. It avoids the formation of solder bridges.

Design tips for solder mask clearance:

• It is recommended that the vias in the solder mask have larger clearances than the hole diameter, especially the small vias. If not required, it is better to remove the solder mask clearances for via holes.
• Solder mask clearance should always be larger than the solder pads, except for solder mask defined pads.
• Solder bridging can be avoided by encroaching the mask opening onto the copper pad or providing barrel relief (solder mask clearance = drill size + 3mils). A mask plugged (a.k.a. mask filled or non-conductive filled via) is also a solution.
• Most of the PCB design software allows you to set the distance between the solder mask and surface elements for the entire board or for individual elements. This parameter is usually called the solder mask expansion and may be positive, zero, or negative. Therefore, suppose the solder mask expansion is zero, and everything is aligned just perfectly then the board would work fine. But in practice, things never align that perfectly. When your solder mask expansion is very narrow then these tiny misalignments can cause it to partially or completely overlap the SMT pads and the through-hole pads. The shift in the solder mask results in the mask on the pad which reduces the footprint of the component. Practically, it is best to specify a minimum tolerance in solder mask expansion that is manufacturable based on your design needs.
• The correct reflow profile is also very important, and DFM is the key to it.

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Silkscreen helps identify PCB components and their orientations, various test points, marks, etc. It is the responsibility of every PCB manufacturer to employ silkscreen guidelines as part of their DFM checklist.

Silkscreen considerations for designers

• Silkscreen to mask spacing: The ink used for silkscreen formation should not be printed over pads or on the PCB surface. If the ink is applied over pads, there is a possibility that it will melt into the solder joint.
• Silkscreen to copper spacing: Copper spacing is defined as the minimum air gap between any two adjacent copper features or traces. Silkscreen should not be overprinted, as it can lead to several problems during soldering, assembly, and inspection tests.
• Silkscreen to hole spacing and rout spacing: Designers must place silkscreen outlines within defined boundaries to avoid overlapping with minimum hole spacing and profile spacing. While implementing silkscreen outlines, designers need to ensure that the silkscreen should not overlay the full component body.
• Line width and text height: There is no recognized standard for deciding the line width and text height. Sierra Circuits can print lines with a minimum of 4 mils. We also recommend using a minimum text height of 25 mils for good readability. It is highly recommended for PCB designers as well as manufacturers not to place silkscreen text on top of the copper layer without a solder mask layer.

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Choosing the right design tool is essential. In good DFM practices, including the desired outcome, we also need to consider the issues that could affect the functioning, cost, and quality of the board before the PCB manufacturing process starts. These design tools combine design tactics and manufacturing processes to realize the precise manufacturability level in the design. The best DFM tool should be able to provide detailed information about how the design choices will impact the outcome/manufacturability of the design. Always discuss with your manufacturer if you have not been formally trained or have not used it very much.

• Keep track of the inaccurate output (stick to the Gerber files).
• Check for tolerances.
• Use different CAD packages for different PCB designs (you cannot manufacture different PCBs in a single batch).
• Give importance to practical practices rather than learning them theoretically (what impact can a small detail make? It can be understood by doing everything in real-time).
• You should know that a useful design tool always provides feedback so that changes could be made.

DFM issues cannot be avoided completely but can be detected in the early design stages. DFM analysis is expensive, but nowadays, we have several DFM tools that provide the same in-depth analysis at a low cost. These tools can be used and deployed easily in the PCB layout process. Design for testing that involves a thorough examination of the board’s electrical conductivity is also a vital aspect to fabricate a flawless board. A good DFM process ensures that the design is not only optimized for electrical performance but can also be manufactured easily on a large production scale without increasing cost, risk, and time factor.

To produce quality PCBs, the designers should know about the latest DFM rules to avoid problems during the initial manufacturing stages. Design for manufacturability is a critical process since board complexity is imposing challenges because of increased density and performance requirements of current and advanced processes and materials.